mirror of
https://github.com/macocianradu/goboy.git
synced 2026-03-18 21:10:07 +00:00
finished first row of opcodes
This commit is contained in:
22
cpu/flags.go
22
cpu/flags.go
@@ -1,6 +1,10 @@
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package cpu
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func Set8BitAddFlags(context op_context, byte1 byte, byte2 byte) byte {
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import (
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"radu.macocian.me/goboy/cpu/operations"
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)
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func Add8BitsAndSetFlags(context op_context, byte1 byte, byte2 byte) byte {
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result := uint16(byte1) + uint16(byte2)
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halfcarry := (byte1&0x0F)+(byte2&0x0F) > 0x0F
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context.cpu.SetNF(false)
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@@ -17,3 +21,19 @@ func Add16BitsAndSetFlags(context op_context, op1 uint16, op2 uint16) uint16 {
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context.cpu.SetCF(result > 0xFFFF)
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return uint16(result)
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}
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func IncAndSetFlags(context op_context, op1 *byte) {
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halfcarry := *op1&0x0F == 0x0F
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context.cpu.SetNF(false)
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context.cpu.SetHF(halfcarry)
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context.cpu.SetZF(*op1 == byte(0))
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operations.INC(op1)
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}
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func DecAndSetFlags(context op_context, op1 *byte) {
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halfcarry := *op1&0x0F == 0x00
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context.cpu.SetZF(*op1 == byte(0))
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context.cpu.SetNF(true)
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context.cpu.SetHF(halfcarry)
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operations.DEC(op1)
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}
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@@ -34,48 +34,33 @@ func INCBC(context op_context) {
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// 0x04 INCB Increment the contents of register B by 1.
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func INCB(context op_context) {
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if context.cpu.B&0x0F == 0x0F {
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context.cpu.SetHF(true)
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} else {
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context.cpu.SetHF(false)
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}
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operations.INC(&context.cpu.B)
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context.cpu.SetZF(context.cpu.B == byte(0))
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context.cpu.SetNF(false)
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IncAndSetFlags(context, &context.cpu.B)
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}
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// 0x05 DECB Decrement the contents of register B by 1.
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func DECB(context op_context) {
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if context.cpu.B&0x0F == 0x00 {
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context.cpu.SetHF(true)
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} else {
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context.cpu.SetHF(false)
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}
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operations.DEC(&context.cpu.B)
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context.cpu.SetZF(context.cpu.B == byte(0))
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context.cpu.SetNF(true)
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DecAndSetFlags(context, &context.cpu.B)
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}
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// 0x06 LD8B Load the 8-bit immediate operand d8 into register B.
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func LD8B(context op_context) {
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operations.LD(&context.cpu.B, memory.Read8(uint(context.immediate)))
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// 0x06 LDBd8 Load the 8-bit immediate operand d8 into register B.
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func LDBd8(context op_context) {
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operations.LD(&context.cpu.B, byte(context.immediate))
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}
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// 0x07 RLCA Rotate the contents of register A to the left. The contents of bit 7 are placed in both the CY flag and bit 0 of register A.
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func RLCA(context op_context) {
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a7 := context.cpu.A>>7 == 1
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operations.Shift(&context.cpu.A)
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a7 := context.cpu.A >> 7
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operations.ShiftLeft(&context.cpu.A)
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context.cpu.A = context.cpu.A | byte(a7)
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context.cpu.SetZF(false)
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context.cpu.SetNF(false)
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context.cpu.SetHF(false)
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context.cpu.SetCF(a7)
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context.cpu.SetCF(a7 == 1)
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}
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// 0x08 LDA16 Store the lower byte of stack pointer SP at the address specified by the 16-bit immediate operand a16, and store the upper byte of SP at address a16 + 1.
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func LDA16(context op_context) {
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// 0x08 LDa16SP Store the lower byte of stack pointer SP at the address specified by the 16-bit immediate operand a16, and store the upper byte of SP at address a16 + 1.
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func LDa16SP(context op_context) {
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operations.LDInMemory8(context.immediate, operations.GetLowerByte(context.cpu.SP))
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operations.LDInMemory8(context.immediate+1, operations.GetHigherByte(context.cpu.SP))
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}
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@@ -85,3 +70,41 @@ func ADDHLBC(context op_context) {
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result := Add16BitsAndSetFlags(context, context.cpu.HL(), context.cpu.BC())
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context.cpu.SetHL(result)
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}
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// 0x0A LDABC Load the 8-bit contents of memory specified by register pair BC into register A.
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func LDABC(context op_context) {
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operations.LDFromMem(&context.cpu.A, uint(context.cpu.BC()))
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}
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// 0x0B DECBC Decrement the contents of register pair BC by 1.
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func DECBC(context op_context) {
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operations.DEC16(&context.cpu.B, &context.cpu.C)
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}
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// 0x0C INCC Increment the contents of register C by 1.
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func INCC(context op_context) {
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IncAndSetFlags(context, &context.cpu.C)
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}
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// 0x0D DECC Decrement the contents of register C by 1.
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func DECC(context op_context) {
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DecAndSetFlags(context, &context.cpu.C)
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}
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// 0x0E LDCd8 Load the 8-bit immediate operand d8 into register C.
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func LDCd8(context op_context) {
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context.cpu.C = byte(context.immediate)
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}
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// 0x0F RRRCA Rotate the contents of register A to the right. That is, the contents of bit 7 are copied to bit 6, and the previous contents of bit 6 (before the copy) are copied to bit 5. The same operation is repeated in sequence for the rest of the register. The contents of bit 0 are placed in both the CY flag and bit 7 of register A.
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func RRRCA(context op_context) {
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a0 := context.cpu.A & 0x01
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operations.ShiftRight(&context.cpu.A)
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context.cpu.A = context.cpu.A | byte(a0)<<7
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context.cpu.SetZF(false)
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context.cpu.SetNF(false)
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context.cpu.SetHF(false)
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context.cpu.SetCF(a0 == 1)
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}
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@@ -1,5 +1,9 @@
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package operations
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func Shift(r1 *byte) {
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func ShiftLeft(r1 *byte) {
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*r1 = *r1 << 1
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}
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func ShiftRight(r1 *byte) {
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*r1 = *r1 >> 1
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}
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@@ -4,9 +4,9 @@ import (
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"testing"
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)
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func TestShift(t *testing.T) {
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func TestShiftLeft(t *testing.T) {
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r1 := byte(0b01010101)
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Shift(&r1)
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ShiftLeft(&r1)
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expected := byte(0b10101010)
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actual := r1
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@@ -15,3 +15,15 @@ func TestShift(t *testing.T) {
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t.Errorf("actual %x != expected %x", actual, expected)
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}
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}
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func TestShiftRight(t *testing.T) {
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r1 := byte(0b01010101)
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ShiftLeft(&r1)
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expected := byte(0b00101010)
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actual := r1
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if actual != expected {
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t.Errorf("actual %x != expected %x", actual, expected)
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}
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}
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@@ -7,6 +7,14 @@ var OpTable = [256]func(context op_context){
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INCBC, //0x03
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INCB, //0x04
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DECB, //0x05
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LD8B, //0x06
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LDBd8, //0x06
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RLCA, //0x07
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LDa16SP, //0x08
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ADDHLBC, //0x09
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LDABC, //0x0A
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DECBC, //0x0B
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INCC, //0x0C
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DECC, //0x0D
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LDCd8, //0x0E
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RRRCA, //0x0F
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}
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7
journal/Day 3 - 2025.06.30.md
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7
journal/Day 3 - 2025.06.30.md
Normal file
@@ -0,0 +1,7 @@
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# For the day:
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- Understand the cpu flags and when they are set
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# Conclusion
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- Wrote helper functions for setting the flags after addition/subtraction
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- Understood when the half-carry flag is set in addtions and subtractions
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- ?The carry flag is not set of INC and DEC operations?
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