added second row of the optable

This commit is contained in:
radumacocian
2025-07-01 18:51:39 +02:00
parent e383b9a85d
commit 16a1c888a7
3 changed files with 119 additions and 5 deletions

View File

@@ -19,8 +19,8 @@ func LDBCd16(context op_context) {
context.cpu.SetBC(context.immediate)
}
// 0x02 LDBCa Store the contents of register A in the memory location specified by register pair BC.
func LDBCa(context op_context) {
// 0x02 LDBCA Store the contents of register A in the memory location specified by register pair BC.
func LDBCA(context op_context) {
operations.LDInMemory8(context.cpu.BC(), context.cpu.A)
return
}
@@ -105,5 +105,4 @@ func RRRCA(context op_context) {
context.cpu.SetNF(false)
context.cpu.SetHF(false)
context.cpu.SetCF(a0 == 1)
}

View File

@@ -18,3 +18,103 @@ func STOP(context op_context) {
//TODO
return
}
// 0x11 LDDEd16 Load the 2 bytes of immediate data into register pair DE.
func LDDEd16(context op_context) {
context.cpu.SetDE(context.immediate)
}
// 0x12 LDDEA Store the contents of register A in the memory speicifed by the register pair DE.
func LDDEA(context op_context) {
operations.LDInMemory8(context.cpu.DE(), context.cpu.A)
return
}
// 0x13 INCDE Increment the contents of register pair DE by 1.
func INCDE(context op_context) {
operations.INC16(&context.cpu.D, &context.cpu.E)
}
// 0x14 INCD Increment the contents of register D by 1.
func INCD(context op_context) {
IncAndSetFlags(context, &context.cpu.D)
}
// 0x15 DECD Decrement the contents of register D by 1.
func DECD(context op_context) {
DecAndSetFlags(context, &context.cpu.D)
}
// 0x16 LDDd8 Load the 8-bit immediate operand d8 into register D.
func LDDd8(context op_context) {
operations.LD(&context.cpu.D, byte(context.immediate))
}
// 0x17 RLA Rotate the contents of register A to the left, through the carry (CY) flag.
func RLA(context op_context) {
a7 := context.cpu.A >> 7
operations.ShiftLeft(&context.cpu.A)
carry := 0
if context.cpu.CF() {
carry = 1
}
context.cpu.A = context.cpu.A | byte(carry)
context.cpu.SetZF(false)
context.cpu.SetNF(false)
context.cpu.SetHF(false)
context.cpu.SetCF(a7 == 1)
}
// 0x18 JRs8 Jump s8 steps from the current address in the program counter (PC). (Jump relative.)
func JRs8(context op_context) {
signedValue := int8(context.immediate & 0x00FF)
context.cpu.PC += uint16(int16(signedValue))
}
// 0x19 ADDHLDE Add the contents of register pair DE to the contents of register pair HL, and store the results in register pair HL.
func ADDHLDE(context op_context) {
result := Add16BitsAndSetFlags(context, context.cpu.DE(), context.cpu.HL())
context.cpu.SetHL(result)
}
// 0x1A LDADE Load the 8-bit contents of memory specified by register pair DE into register A.
func LDADE(context op_context) {
operations.LDFromMem(&context.cpu.A, uint(context.cpu.DE()))
}
// 0x1B DECDE Decrement the contents of register pair DE by 1.
func DECDE(context op_context) {
operations.DEC16(&context.cpu.D, &context.cpu.E)
}
// 0x1C INCE Increment the contents of register E by 1.
func INCE(context op_context) {
IncAndSetFlags(context, &context.cpu.E)
}
// 0x1D DECE Decrement the contents of register E by 1.
func DECE(context op_context) {
DecAndSetFlags(context, &context.cpu.E)
}
// 0x1E LDEd8 Load the 8-bit immediate operand d8 into register E.
func LDEd8(context op_context) {
context.cpu.E = byte(context.immediate)
}
// 0x1F RRA Rotate the contents of register A to the right, through the carry (CY) flag.
func RRA(context op_context) {
a0 := context.cpu.A & 0x01
operations.ShiftRight(&context.cpu.A)
carry := 0
if context.cpu.CF() {
carry = 1
}
context.cpu.A = context.cpu.A | byte(carry)<<7
context.cpu.SetZF(false)
context.cpu.SetNF(false)
context.cpu.SetHF(false)
context.cpu.SetCF(a0 == 1)
}

View File

@@ -3,7 +3,7 @@ package cpu
var OpTable = [256]func(context op_context){
NOOP, //0x00
LDBCd16, //0x01
LDBCa, //0x02
LDBCA, //0x02
INCBC, //0x03
INCB, //0x04
DECB, //0x05
@@ -19,4 +19,19 @@ var OpTable = [256]func(context op_context){
RRRCA, //0x0F
STOP, //0x10
LDDEd16, //0x11
LDDEA, //0x12
INCDE, //0x13
INCD, //0x14
DECD, //0x15
LDDd8, //0x16
RLA, //0x17
JRs8, //0x18
ADDHLDE, //0x19
LDADE, //0x1A
DECDE, //0x1B
INCE, //0x1C
DECE, //0x1D
LDEd8, //0x1E
RRA, //0x1F
}